‘This is how AI should be used’ — OpenAI head of hardware breaks down the AI-assisted design of its Jalapeño ASIC

OpenAI’s Jalapeño ASIC is a seismic shift for the industry, not because of its efficiency or performance, but because of how it was designed. The company was clear from the jump that AI played a big role in the design process of Jalapeño, not only for the hardware itself, but also in the co-design with OpenAI’s software stack, allowing the ASIC to go from initial register-transfer level (RTL) to tapeout in a matter of just nine months.

From concept to reveal, the timeline was less than two years. Richard Ho, head of hardware at OpenAI, says the timeline “established a new baseline,” and that the industry is already knocking on OpenAI’s door to learn how the company pulled it off. Go deeper with TH Premium: AI and data centers(Image tomshardware.com/pc-components/cooling/the-data-center-cooling-state-of-play-2025-liquid-cooling-is-on-the-rise-thermal-density-demands-skyrocket-in-ai-data-centers-and-tsmc-leads-with-direct-to-silicon-solutions?utm_source=edit-links&utm_medium=boxout&utm_term=datacenter” target=”_blank”>The data center cooling state of playThe custom AI ASIC state of play America’s AI chip rules keep changing — and the rest of the world is paying the priceGTC 2026: Ian Buck press Q&A transcript — VP of Hyperscale and HPC speaks out on shelving CPX and shipping LPU decode this yearDemand for data center CPUs has surged, and AI agents are responsible“The way I like to think about it is, we’ve established a new baseline. In the old baseline, you’re talking 18 months to two years, roughly. Often that’s even with some existing IP or some more legacy architecture design,” Ho told Tom’s Hardware Premium in an interview. “We’re starting from scratch here. We had nothing. There’s not a line of code here to refer to. What we’ve established is that there’s a new baseline that you can do with a very talented team with the help of AI. Now, does it get shorter? It depends on what you’re trying to do.” AI usage in chip design is nothing new, predating the era of LLMs entirely. The largest Electronic Design Automation (EDA) companies, Cadence and Synopsys, have a portfolio of AI-assisted chip design tools that have been around for several years. The models OpenAI used were its own internal models, however, and it leveraged both existing EDA tools and its new AI-assisted engineering workflow. The engineering team used OpenAI’s agentic coding platform, Codex, for the Jalapeño design. “But we think that every engineering team in chip design should be able to use this as a new baseline, because it’s a proof point that the models that are in use — the AI models for us is mostly Codex, Sol, the one before Sol, and now we’re moving on to Astra.